This disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure including crystalline compound semiconductor material grown on a crystalline semiconductor substrate wherein the compound semiconductor material and the substrate semiconductor material are lattice mismatched. This disclosure also provides a method of fabricating such a semiconductor structure.
Silicon is the basic material for present solid-state electronics, and processing techniques have been evolved for decennials. Hence, most electronic integrated circuit devices are based on silicon. However, the relatively low charge carrier mobility and its indirect band gap are disadvantages and limit the use of silicon in particular in opto-electronic applications.
A monolithic integration of compound semiconductors on silicon wafers is desirable and has extensively been investigated in the past. Several problems need to be overcome when compound semiconductors and conventional silicon technologies are to be combined. First, there is a large lattice mismatch between a crystalline silicon substrate and compound semiconductor crystals. Further, there is a thermal expansion coefficient mismatch between the (silicon) wafer material and the active compound semiconductor material. Additionally, a structural mismatch between diamond-like structures and zincblende structures may occur. It is an overall goal to achieve high crystalline quality over various monolithic layers for compound semiconductor on a foreign substrate such as silicon.
In an effort to achieve high crystalline quality in crystalline material layers that show a lattice mismatch, several methods have been developed. For example, direct epitaxy of blanket layers allow for a gradual transition from one lattice parameter to the next. However, relatively thick transition layers are needed to reduce the defect density considerably.
In US 2002/0153524 A1, a crystalline silicon substrate is provided with a perovskite stack comprising perovskite oxide materials. On the top of the stack, a crystalline material having a lattice mismatch with the substrate material is deposited. At the interface between the perovskite stack and the substrate, a strain relaxation occurs which reduces defects in the top compound material.
Other techniques to combine compound semiconductor materials with conventional silicon wafers include bonding techniques. In direct wafer bonding, a compound hetero structure is fabricated on a donor wafer wherein the donor wafer material is eliminated after bonding with the conventional silicon wafer. This makes the bonding technology relatively expensive. Further, bonding is limited to the size of costly compound substrate wafers.
Another approach for combining lattice-mismatched materials, such as compound semiconductors with silicon substrates, is the aspect ratio trapping approach. Aspect ratio trapping (ART) refers to a technique where crystalline defects are terminated at non-crystalline, for example, dielectric sidewalls. U.S. Pat. No. 8,173,551 B2 discloses a method where a silicon substrate is covered with a dielectric layer defining trenches through to the substrate material. In the trenches, epitaxial films of a compound material are deposited wherein particular geometries of the growth front are realized. The aspect ratio of the trenches needs to be large enough to terminate the defects that nucleate at the silicon-compound interface so that higher parts of the crystalline compound show a low crystalline defect density. Some approaches of the ART technique teach the use of Germanium microcrystals grown in silicon oxide trenches on a silicon substrate with a gallium arsenide film on top.